x86-64 · Arm AArch64 · RISC-V · Cross-Architecture Systems

The Processor Architecture Atlas Series is a four-volume, large-format visual reference created for operating-system developers, compiler engineers, system programmers, assembly-language developers, performance specialists, and everyone working close to the hardware.

Designed in a spacious A3 portrait format, the series transforms complex processor documentation into structured maps, precise tables, register diagrams, instruction summaries, encoding layouts, memory models, privilege charts, interrupt flows, synchronization references, and concise technical explanations.

Rather than treating each architecture in isolation, the series presents three major processor families individually and then brings them together in a dedicated comparison volume. This allows readers to understand not only how each architecture works, but also how equivalent concepts differ across x86-64, Arm AArch64, and RISC-V.

Volume 1 — The x86-64 Architecture Atlas

A comprehensive visual reference to the x86-64 programming and system architecture.

This volume covers general-purpose registers and their overlapping forms, RFLAGS, control registers, segmentation, descriptor tables, addressing modes, instruction prefixes, ModR/M and SIB encoding, integer instructions, control flow, stack operations, paging, exceptions, interrupts, system calls, atomic instructions, memory ordering, SIMD, AVX, AVX-512, AMX, feature discovery, debugging, and major calling conventions.

It is designed to make the complexity and historical depth of x86-64 easier to understand and navigate.

Volume 2 — The Arm AArch64 Architecture Atlas

A structured reference to the modern Arm A-profile architecture and the AArch64 execution state.

This volume explains X and W registers, SP, PC, PSTATE, condition flags, system registers, fixed-width instruction encoding, load/store addressing, branches, procedure calls, exception levels, virtual memory, translation tables, interrupt handling, barriers, atomic operations, cache maintenance, NEON, SVE, SVE2, SME, feature identification, and the AAPCS64 calling convention.

It provides a clear view of the architecture used across mobile devices, servers, embedded platforms, and modern high-performance systems.

Volume 3 — The RISC-V Architecture Atlas

A detailed visual guide to the modular and extensible RISC-V architecture.

This volume covers integer registers and ABI names, instruction formats, the base ISA, privilege modes, control and status registers, loads, stores, branches, jumps, multiplication, division, atomic operations, floating-point extensions, compressed instructions, vector processing, bit manipulation, cryptographic extensions, virtual memory, physical memory protection, traps, interrupts, memory ordering, fences, debugging, performance counters, and the RISC-V psABI.

Special attention is given to RISC-V’s modular extension model and the relationship between the ISA, privileged architecture, profiles, and platform specifications.

Volume 4 — The Cross-Architecture Systems Atlas

A direct comparison of x86-64, Arm AArch64, and RISC-V from a low-level software perspective.

This volume aligns equivalent registers, instructions, flags, calling conventions, stack layouts, addressing models, instruction encodings, privilege systems, page-table structures, exceptions, interrupts, atomic operations, memory-ordering rules, vector architectures, object formats, system calls, and compiler-backend requirements.

It helps readers translate concepts between architectures and understand why similar operations may require very different implementations.

The comparison volume is especially valuable for:

  • Operating-system and kernel developers
  • Compiler and assembler designers
  • Virtual-machine and emulator developers
  • Cross-platform library authors
  • Reverse engineers
  • Performance and toolchain specialists
  • Students of computer architecture and low-level programming

A Practical Visual Reference

The series is designed as a technical atlas rather than a conventional textbook. Each page focuses on rapid access to information through:

  • Large comparative tables
  • Register and bit-field diagrams
  • Instruction-family maps
  • Encoding breakdowns
  • Memory-translation charts
  • Privilege and exception flows
  • Synchronization references
  • ABI and stack-frame layouts
  • Concise usage notes
  • Links to official English specifications

The goal is to provide a precise and practical reference that reduces the need to search through many separate manuals when studying or implementing low-level software.