The x86-64 instruction set is powerful, mature, and remarkably flexible, but its encoding system is also one of the most detailed and layered in modern computing. A single assembly instruction may involve register identifiers, operand-size rules, legacy prefixes, REX, VEX, or EVEX fields, opcode maps, ModR/M and SIB bytes, displacements, immediate values, condition codes, processor features, and object-format relocations.
Understanding each element separately is important. Being able to connect them quickly and correctly is essential.
This volume was created as a practical desk-side reference for programmers and engineers who need direct access to the structural rules behind x86-64 machine-code encoding. It is intended for assembler and disassembler developers, compiler and JIT engineers, binary-analysis and reverse-engineering specialists, debugger authors, systems programmers, and anyone who must inspect, generate, validate, or understand x86-64 instruction bytes.
Unlike a conventional textbook, this book is optimized primarily for lookup rather than continuous reading. Its chapters are organized around the decisions an encoder or decoder must make:
- Identify the required instruction form.
- Determine operand and address sizes.
- Select the appropriate prefix family.
- Choose the opcode map and opcode.
- Construct the ModR/M and SIB fields.
- Encode displacements and immediate values.
- Validate flags, processor features, and relocation requirements.
The tables follow this workflow and provide a compact map of the most important encoding structures. They cover general-purpose, system, vector, mask, and tile registers; operand-size and address-size behavior; legacy, REX, VEX, and EVEX prefixes; opcode maps and opcode-extension groups; all ModR/M and SIB byte values; effective-address construction; immediate and relative-offset rules; RFLAGS and condition codes; SIMD decorators; CPU feature families; and relocation types across major object formats.
Special attention is given to cases that frequently cause implementation errors, including the incompatibility of high-byte registers with REX prefixes, the special encoding behavior of RBP, R13, RSP, and R12, RIP-relative addressing, displacement-width selection, sign extension, mandatory-prefix interpretation, VEX and EVEX field inversion, and the distinction between encoded field width and architectural operand width.
The appendices provide printable quick-reference sheets, representative golden encoding vectors, NASM directives, output-format guidance, and implementation checklists. These resources are intended to remain beside the development workstation and reduce repeated searches through large architecture manuals.
This book is the fifth volume in the ForgeVM x86-64 Instruction Encoding Technical Reference Series and is designed as the printable lookup companion to Volumes 1–4. While the earlier volumes explain instruction encoding progressively, this atlas gathers the most frequently needed values, matrices, rules, and cross-references into one concentrated engineering reference.
This volume does not attempt to replace the official Intel and AMD architecture manuals or a verified instruction-form database. The x86-64 architecture continues to evolve through technologies such as Intel APX, AVX10, AMX, and other processor-specific extensions. Instruction availability, reserved encodings, exceptions, privilege requirements, feature dependencies, and future behavior must always be confirmed against current primary specifications before production use.
The purpose of this atlas is therefore not to reduce the architecture to oversimplified rules, but to make its structure visible, searchable, and usable. It transforms scattered encoding details into a consistent reference that can support both manual investigation and automated implementation.
Whether you are examining a few bytes in a debugger, writing a new encoder, validating compiler output, implementing relocation handling, or studying how assembly operands become machine instructions, I hope this volume provides a clear and reliable path through the x86-64 encoding system.